1) Field of the Invention
The present invention relates to a structure of a semiconductor device, and more particularly to a structure of a bonding pad in a semiconductor device.
2) Description of the Prior Art
FIG. 8 is a plan view and FIG. 9 is a sectional view of a conventional semiconductor device. Both are enlarged views particularly showing a region having bonding pads in a semiconductor device (see for example, Japanese Patent Application Laid-Open No. 5-29377). In these Figures, the semiconductor device includes a semiconductor substrate 101, an insulating film 102 deposited on the semiconductor substrate 101, a plurality of lead conductors 103 disposed on the insulating film 102 at equal intervals, an interlayer insulating film 104 deposited on the insulating film 102 and the leads 103, a plurality of lower electrode pads 105 electrically connected to respective leads 103, and a plurality of upper electrode pads 106 respectively deposited on the lower electrode pads 105 through respective through holes and having larger surface areas than the lower electrode pads 105, and a passivation film 107.
As seen in FIG. 8, there are disposed outer circumferential pads 108 formed at the area nearest to the edge, i.e., the outer circumference, of the semiconductor chip, and inner circumferential pads 109 formed on the inner circumference. The inner circumferential pads 109 are disposed and formed at equal intervals of a given pitch. The pitch of the inner circumferential pads 109 is equal to the sum of the width of a lead, e.g., 103a and of one pad, by way of the lead connected to one of the outer circumferential pads 108.
Further, FIGS. 10 and 11 show a structure of another conventional bonding pad of a semiconductor device (see for example, Japanese Patent Application Laid-Open No. 4-316337). As with the aforementioned prior art, on the outer and inner circumferences along the edge of a semiconductor substrate 101, outer and inner circumferential pads 108 and 109 are disposed at equal intervals in zigzag fashion. While the outer circumferential pads 108 are disposed and formed on the semiconductor substrate 101, the inner circumferential pads 109 are disposed and formed on the insulating films 102a and 102bdeposited on the semiconductor substrate 101. As seen from the sectional view of FIG. 11, the surface of the outer circumferential pad 108 and the surface of the inner circumferential pad 109 differ from each other in height.
In the semiconductor device with pads thus disposed and formed, a plurality of arrays of pads are disposed and formed in a zigzag fashion along the edge of the semiconductor chip. Thus, the pad pitch is effectively reduced.
However, as seen from the layout of the conventional semiconductor device as shown in FIG. 8 and 9, the surfaces of the upper electrode pads 106 in the outer and inner circumferential pads 108 and 109 are not flat due to the unevenness on the surface of the lower layer. Therefore, pads may be cracked by a bonding pressure and the lower metal lead may also be cracked or broken by the stress applied to the lower lead. Thus, there is a problem with reliability.
Also, as seen from the layout of the conventional semiconductor device shown in FIGS. 10 and 11, the heights of the inner and outer circumferential pads 109 and 108 differ from each other. Therefore, the setting of the height of a bonder must be made with respect to the layout of the pads at the time of bonding. Thus, there is the problem that the number of processes, manufacturing cost, and processing time are increased.